During semiconductor manufacturing processes, layers of various materials are deposited or grown on a wafer or die, one after the other. After many of the layers are deposited, lithographic processing techniques are used to transfer patterns to the surface layer or layers. In order for the finished product to operate properly, the pattern of each layer must be precisely aligned to the patterns of the other wafers on the layer, since misalignment of a layer with respect to a previous layer may be catastrophic to performance. One lithographic technique that is commonly used is a step-and-repeat pattern transfer system ("stepper") that involves imaging several exposures of portions of the wafer to cover an entire wafer surface.
To achieve perfect alignment, alignment marks are formed on the wafer and are used by the steppers, so that in each lithographic step, the mask will be properly aligned according to the marks in the previous layers before exposing the wafer. In typical systems, four marks are used, circumferentially distributed around the periphery of the wafer, although alignment can be made with fewer or greater than four marks, and can be placed on other parts of the wafer.
It is desirable for alignment marks to have sharp edges, and a depth that allows the mark to be recognized by the stepper in order to make the mark useful as an alignment tool. A typical depth of the mark required by conventional steppers manufactured by ASM Lithography is 1200 .ANG.. Marks required by steppers by other stepper manufacturers may need a different mark depth. If the mark region has edges that are too close to one another, or if the mark contains material that is discolored, the wrong edge may be selected by the stepper so that misalignment will result. Alignment is particularly critical in processes for manufacturing extremely small devices, such as sub-micron devices. However, residual matter within a mark can blur the resolution of the mark and prevent this necessary accurate alignment. For example, residual nitride or other materials employed in semiconductor fabrication can remain near the edges or in the middle of the mark, and will detrimentally affect the ability of a stepper to align subsequent exposures with these marks.
A relatively recent technique for isolating an active region in a semiconductor chip is known as shallow trench isolation. In this technique, a shallow trench is formed around an active region to isolate this active region from other regions of the chip. Although shallow trench isolation has proven to be a valuable technique, the formation of marks in conjunction with the shallow trench isolation technique leaves residual material (e.g., nitride) within the marks. As stated earlier, the residual nitride in the marks interferes with proper working of the alignment system, causing frequent alignment failures and resultant reworks and scraps.
The formation of a mark according to the prior art in conjunction with a shallow trench isolation process is depicted in FIGS. 1-8, to illustrate the above-described problems with residual nitride. The placement of marks on a substrate is commonly performed before the implementation of the semiconductor devices, so that the location of the devices relative to the marks can be accurately controlled. In FIG. 1, semiconductor substrate 10 is cleaned, and an oxide layer 12 is grown or deposited on the semiconductor substrate 10 to approximately 150 .ANG.. This oxide is needed to avoid subsequent photoresist process being directly applied on the Si substrate. Next, a photoresistive material (commonly called resist) 14 that is patterned by a lithographic process is spun on the oxide layer 12. The lithographic process transfers an alignment pattern on the resist 14, with the patterns being the openings 13 in the resist. The subsequent etching process (called zero layer etch) etches the oxide layer 12 and the substrate 10 in the open areas leaving the unopened areas untouched. The etching may be performed anisotropically, such as by a reactive ion etch (RIE) process, to form substantially orthogonal sidewalls, that is, sidewalls normal to both the plane of the substrate surface prior to the etch and normal to the bottom of the mark 16, as depicted in FIG. 2. The photoresistive mask 14 is then removed, leaving the oxide 12 and substrate 10 with a 1200 .ANG. deep trench in the substrate 102. After etching, the oxide layer 12 is removed, leaving the resulting structure with a mark 16 in the substrate 10 depicted in FIG. 3. The mark 16 will then be used in subsequent processing steps in order to align the masks.
The following described steps, depicted in FIGS. 4-8, are performed in order to create a shallow isolation trench (typically 3000 .ANG. deep). However, only the mark is depicted in FIGS. 4-8 in order to illustrate the effect of the shallow trench isolation manufacturing process on the mark 16.
From FIG. 3, an oxide layer 18 is thermally grown on the substrate 10. The oxide layer is approximately 150 .ANG. thick, and covers the die surface, including the mark 16. The resulting structure is a semiconductor substrate 10 having a mark 16 with a depth of 1200 .ANG. covered by a thin oxide layer 18 thickness of approximately 150 .ANG., as depicted in FIG. 4. This oxide is needed to avoid direct contact of the subsequent nitride deposition with Si substrate.
In FIG. 5, a nitride layer 20 (Si.sub.3 N.sub.4) is deposited on the oxide layer 108 to a thickness of approximately 1700 .ANG.. The nitride layer 20 settles into the mark 16 and a depression therefore forms in the nitride layer 20 over this mark 16.
A number of processing steps are then performed in order to create the shallow trenches, such as covering the nitride layer with a source/drain mask which is patterned by a lithographic process. The area over the mark 16 will be covered at this time. Etching is performed in the open areas of the mask to create the trenches around the active device regions as desired. Once the etches have been performed and the shallow trenches are created, the mask is removed from the nitride layer, once again leaving the structure of FIG. 5.
The next step in the shallow trench isolation process is the depositing of a TEOS layer 22 (tetraethyl orthosilane) with a depth of approximately 6200 .ANG. on the nitride layer 20. The resulting structure in the region of the mark 16 is depicted in FIG. 6. The TEOS layer 22 is then etched with a planarization mask, so that areas on top of the nitride layer 20 are exposed except in the active device regions. The area over the mark 16 is exposed as well. The TEOS layer 22 is then removed with an etch. This removes most of the TEOS layer 22, as shown in FIG. 6a. Chemical mechanical planarization (CMP) is employed to remove the remainder of the TEOS layer 22, with the nitride layer 20 acting as a polish stop (FIG. 7). Because of the nature of the CMP process, the remainder of the TEOS on a flat surface can be completely polished away, those in the depressed mark regions cannot be consistently polished away, resulting in residual TEOS 22 within the depression in the nitride layer 20. This residual TEOS 22 creates a problem in the next step, which is the removal of the nitride layer 20.
Hot phosphoric acid is applied to remove the nitride layer 20. Although nearly all the nitride layer 20 is removed, the TEOS 22 that remained in the depression in the nitride layer 20 serves to prevent complete removal of the nitride layer 20 within the mark 16. As depicted in FIG. 8, the residual TEOS 22 effectively shields the nitride layer 20 underneath the residual TEOS 22. This creates structures, such as the columns of nitride 20 in FIG. 8. Other irregular shapes may arise as well, depending on the thickness and the extent of the residual TEOS 22. Nitride remaining within the mark 16 presents a discoloration that confuses a stepper trying to align on the mark 16. Also, the stepper is likely to have problems with determining the location of the edges 24 of the mark 16, due to the edges present on the columns 20 of the residual nitride within the mark 16.
As demonstrated above, the shallow trench isolation technique has a deleterious effect on alignment marks by causing nitride to remain within the alignment marks. This results in misalignment by the stepper and therefore lowers product yield.